1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device.
2. Description of Related Art
Various three-dimensional structures, such as a multilayer interconnect structure and a stacked DRAM memory cell structure, have been adopted in a semiconductor device due to the miniaturization and densification thereof. In such a three-dimensional structure, there is provided a plug for connecting an upper-layer side conductive portion and a lower-layer side conductive portion through an interlayer insulating film.
For example, JP2008-192681A discloses in a stacked memory cell of a DRAM, a structure in which a cell contact plug for connection to a transistor provided on a semiconductor substrate and a capacitance contact plug for connection to an upper-layer side capacitor are connected to each other, and a structure in which a cell contact plug for connection to a transistor provided on a semiconductor substrate and a bit contact plug for connection to an upper-layer side bit line are connected to each other.
On the other hand, plugs are usually formed in the following way. First, a hole is formed in an interlayer insulating film, and a barrier film is formed inside this hole. Next, a conductive film is formed so as to fill this hole. After that, portions of the barrier film and conductive film outside the hole are removed to obtain an intended plug.
For example, JP2006-66642A discloses a plug formation method including: forming a titanium nitride layer as a barrier film inside a hole provided in an interlayer insulating film; and forming a tungsten layer so as to fill this hole. In this method, the tungsten layer is formed by a method of CVD film formation using a fluorine-containing material, and then a treatment is performed to remove fluorine from the tungsten layer.